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? semiconductor components industries, llc, 2008 march, 2008 - rev. 9 1 publication order number: mc100ep016a/d mc100ep016a 3.3 v?ecl 8-bit synchronous binary up counter description the mc100ep016a is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. architecture and operation are the same as the eclinps ? family mc100e016 with higher operating speed. the counter features internal feedback to tc gated by the tcld (terminal count load) pin. when tcld is low (or left open, in which case it is pulled low by the internal pulldowns), the tc feedback is disabled, and counting proceeds continuously, with tc going low to indicate an all-one state. when tcld is high, the tc feedback causes the counter to autom atically reload upon tc = low, thus functioning as a programmable counter. the qn outputs do not need to be terminated for the count function to operate properly. to minimize noise and power, unused q outputs should be left unterminated. cout and cout provide differential outputs from a single, non-cascaded counter or divider application. cout and cout should not be used in cascade configuration. only tc should be used for a counter or divider cascade chain output. a differential clock input has also been added to improve performance. the 100 series contains temperature compensation. features ? 550 ps typical propagation delay ? operation frequency > 1.3 ghz is 30% faster than mc100ep016 ? pecl mode operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = -3.0 v to -3.6 v ? open input default state ? safety clamp on clock inputs ? internal tc feedback (gated) ? addition of cout and cout ? 8-bit ? differential clock input ? v bb output ? fully synchronous counting and tc generation ? asynchronous master reset ? pb-free packages are available lqfp-32 fa suffix case 873a marking diagrams* *for additional marking information, refer to application note and8002/d. http://onsemi.com mc100 ep016a awlyywwg a = assembly location wl = wafer lot yy = year ww = work week g or = pb-free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information 32 1 mc100 ep016a awlyyww 1 qfn32 mn suffix case 488am
mc100ep016a http://onsemi.com 2 v ee 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 mc100ep016a cout cout tc v cc p7 p6 p5 v cc q2 q1 q0 v ee mr ce pe v cc tcld q7 q6 q5 q4 v cc p4 p3 p2 p1 p0 clk v bb clk figure 1. 32-lead lqfp pinout (top view) q3 warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. v ee 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 cout cout tc v cc p7 p6 p5 v cc q2 q1 q0 v ee mr ce pe v cc q6 v cc p4 p3 p2 p1 p0 cl k v bb cl k q4 q5 q7 tcld q3 figure 2. 32-lead qfn pinout (top view) mc100ep016a exposed pad (ep) table 1. pin description pin function p0-p7 ecl parallel data (preset) inputs q0-q7 ecl data outputs ce * ecl count enable control input pe * ecl parallel load enable control input mr* ecl master reset clk*, clk * ecl differential clock tc ecl terminal count output tcld* ecl tc-load control input cout, cout ecl differential output v cc positive supply v ee negative supply v bb reference voltage output ep the exposed pad (ep) on the qfn-32 package bottom is thermally connected to the die for improved heat-sinking conduit. the pad is electrically connected to v ee . *pins will default low when left open.
mc100ep016a http://onsemi.com 3 table 2. function table ce pe tcld mr clk function x l l h x x l h h h x x x l h x x x l l l l l h z z z z zz x load parallel (pn to qn) continuous count count; load parallel on tc = low hold masters respond, slaves hold reset (qn : = low, tc : = high) zz = clock pulse (high-to-low) z = clock pulse (low-to-high) table 3. function table function pe ce mr tcld clk p7-p4 p3 p2 p1 p0 q7-q4 q3 q2 q1 q0 tc cout cout load count l h h h h x l l l l l l l l l x l l l l z z z z z h x x x x h x x x x h x x x x l x x x x l x x x x h h h h l h h h h l h h h h l l l h h l l h l h l h h h l h h h h l h l l l h l load hold l h h x h h l l l x x x z z z h x x h x x h x x l x x l x x h h h h h h h h h l l l l l l h h h h h h l l l load on terminal count h h h h h h l l l l l l l l l l l l h h h h h h z z z z z z h h h h h h l l l l l l h h h h h h h h h h h h l l l l l l h h h h h h h h h l l h h h h h h l l h h h h l h l h l h l h h l h h h h h l h h h l l h l l l reset x x h x x x x x x x l l l l l h h l
mc100ep016a http://onsemi.com 4 figure 3. 8\bit binary counter logic diagram note that this diagram is provided for understanding of logic operation only. it should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay . p 1 slave master 5 tc q 1 q 0 p7 q 6 q 5 q 4 q 3 q 2 q 1 ce q 0 bit 1 ce q 0 q0m q0m pe tcld ce p 0 mr clk bit 7 bits 2-6 q 7 clk cout cout bit 0 v bb v ee
mc100ep016a http://onsemi.com 5 table 4. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb-free pkg lqfp-32 qfn-32 level 2 n/a level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 1226 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 5. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v -6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 -6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range -40 to +70 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 74 61 c/w c/w jc thermal resistance (junction-to-case) standard board 32 lqfp 12 to 17 c/w ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm qfn-32 qfn-32 31 27 c/w c/w jc thermal resistance (junction-to-case) 2s2p qfn-32 12 c/w t sol wave solder pb pb-free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
mc100ep016a http://onsemi.com 6 table 6. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 2) symbol characteristic -40 c 25 c 70 c unit min typ max min typ max min typ max i ee power supply current 130 170 210 130 177 210 130 180 210 ma v oh output high voltage (note 3) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (single-ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single-ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to -0.3 v. 3. all loading with 50 ohms to v cc -2.0 volts. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 7. 100ep dc characteristics, necl v cc = 0 v, v ee = -3.6 v to -3.0 v (note 5) symbol characteristic -40 c 25 c 70 c unit min typ max min typ max min typ max i ee power supply current 130 170 210 130 177 210 130 180 210 ma v oh output high voltage (note 6) -1145 -1020 -895 -1145 -1020 -895 -1145 -1020 -895 mv v ol output low voltage (note 6) -1945 -1820 -1695 -1945 -1820 -1695 -1945 -1820 -1695 mv v ih input high voltage (single-ended) -1225 -880 -1225 -880 -1225 -880 mv v il input low voltage (single-ended) -1945 -1625 -1945 -1625 -1945 -1625 mv v bb output voltage reference -1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 7) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. all loading with 50 ohms to v cc -2.0 volts. 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100ep016a http://onsemi.com 7 table 8. ac characteristics v ee = -3.0 v to -3.6 v; v cc = 0 v or v cc = 3.0 v to 3.6 v; v ee = 0 v (note 8) symbol characteristic -40 c 25 c 70 c unit min typ max min typ max min typ max f count maximum frequency count & division modes q, tc , cout/cout 1.3 1.5 1.2 1.4 1.2 1.3 ghz t plh t phl propagation delay clk to q mr to q clk to tc mr to tc clk to cout/cout mr to cout/cout 350 400 350 400 475 450 511 550 511 555 705 720 650 700 650 700 850 850 400 400 400 400 500 500 550 570 550 570 745 760 700 750 700 750 900 900 480 450 480 520 550 570 610 630 610 635 825 830 780 820 780 820 1000 950 ps t s setup time p0 p1 to p4 p5 to p7 ce pe tcld 400 300 250 500 500 550 240 140 80 320 315 355 400 300 250 500 500 550 240 135 65 330 320 365 400 300 250 500 500 550 245 125 55 340 325 380 ps t h hold time p0 p1 to p4 p5 to p7 ce pe tcld 100 50 150 600 625 525 -145 -160 -105 380 465 320 100 50 150 600 625 525 -155 -170 -110 410 500 325 100 50 150 600 625 525 -170 -180 -115 450 535 340 ps t jitter clock random jitter (rms, 1000 waveforms) 2.6 8.5 2.5 8.0 2.5 8.0 ps t rr reset recovery time 400 195 400 205 400 220 ps t pw minimum pulse width clk minimum pulse width mr 385 550 334 380 416 550 357 380 416 550 385 380 ps t r , t f output rise/fall times 20% - 80% 90 180 320 100 190 320 125 215 450 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc -2.0 v.
mc100ep016a http://onsemi.com 8 applications information cascading multiple ep016a devices for applications which call for larger than 8\bit counters multiple ep016as can be tied together to achieve very wide bit width counters. the active low terminal count (tc ) output and count enable input (ce ) greatly facilitate the cascading of ep016a devices. two ep016as can be cascaded without the need for external gating, however for counters wi der than 16 bits external or gates are necessary for cascade implementations. figure 4 below pictorially illustrates the cascading of 4 ep016as to build a 32\bit high frequency counter. note the ep01 gates used to or the terminal count outputs of the lower order ep016as to control the counting operation of the higher order bits. when the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant ep016a is set in its count mode and will count one binary digit upon the next positive clock transition. in addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. therefore, for an ep016a in the chain to count, all of the lower order terminal count outputs must be in the low state. the bit width of the counter can be increased or decreased by simply adding or subtracting ep016a devices from figure 4 and maintaining the logic pattern illustrated in the same figure. the maximum frequency of operation for a cascaded counter chain is set by the propagation delay of the tc output, the necessary setup time of the ce input, and the propagation delay through the or gate controlling it (for 16-bit counters the limitation is only the tc propagation delay and the ce setup time). figure 4 shows ep01 gates used to control the count enable inputs, however, if the frequency of operation is slow enough, a lvecl or gate can be used. using the worst case guarantees fo r these parameters. figure 4. 32\bit cascaded ep016a counter clk p0 to p7 tc clk p0 to p7 tc clk ep01 p0 to p7 p0 to p7 msb ep016 q0 to q7 q0 to q7 q0 to q7 ep016 q0 to q7 ep016 pe ce lsb ep016 pe ce load lo clk clk clk ep01 tc clk pe ce clk tc clk pe ce clk note that this assumes the trace delay between the tc outputs and the ce inputs are negligible. if this is not the case estimates of these delays need to be added to the calculations. programmable divider the ep016a has been designed with a control pin which makes it ideal for use as an 8\bit programmable divider. the tcld pin (load on terminal count) when asserted reloads the data present at the parallel input pin (pn's) upon reaching terminal count (an all 1s stat e on the outputs). because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. figure 5 below illustrates the input conditions necessary for utilizing the ep016a as a programmable divider set up to divide by 113.
mc100ep016a http://onsemi.com 9 applications information (continued) h l h hlllhhhh tc pe ce tcld clk p7 p6 p4 p3 p2 p1 p0 p5 q7 q6 q4 q3 q2 q1 q0 q5 figure 5. mod 2 to 256 programmable divider clk cout cout to determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. as an example for a divide ratio of 113: pn's = 256 - 113 = 8f 16 = 1000 1111 where: p0 = lsb and p7 = msb forcing this input condition as per the setup in figure 5 will result in the waveforms of figure 6. note that the tc output is used as the divide output and the pulse duration is equal to a full clock period. for even divide ratios, twice the desired divide ratio can be loaded into the ep016a and the tc output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. table 9. preset values for various divide ratios divide ratio preset data inputs p7 p6 p5 p4 p3 p2 p1 p0 2 h h h h h h h l 3 h hhhhhlh 4 h hhhhhl l 5 h hhhhlhh ? ? ??????? ? ? ??????? 112 h llhllll 113 h l l lhhhh 114 h l l lhhh l ? ? ??????? ? ? ??????? 254 l lllllhl 255 l llllllh 256 l l l l l l l l a single ep016a can be used to divide by any ratio from 2 to 256 inclusive. if divide ratios of greater than 256 are needed multiple ep016as can be cascaded in a manner similar to that already discussed. when ep016as are cascaded to build larger dividers the tcld pin will no longer provide a means for loading on terminal count. because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the tc pins must be used for multiple ep016a divider chains. ??? pe ??? ??? clk tc load divide by 113 load 1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111 figure 6. divide by 113 ep016a programmable divider waveforms
mc100ep016a http://onsemi.com 10 applications information (continued) ep01 q0 to q7 p0 to p7 clk tc pe ce figure 7. 32\bit cascaded ep016a programmable divider lo clk clk clk msb lsb ep016 ep01 ep01 q0 to q7 q0 to q7 q0 to q7 q0 to q7 p0 to p7 p0 to p7 p0 to p7 ep016 ep016 ep016 clk tc pe ce clk clk tc pe ce clk clk tc pe ce clk figure 7 shows a typical block diagram of a 32\bit divider chain. once again to maximize the frequency of operation ep01 or gates were used. for lower frequency applications a slower or gate could replace the ep01. note that for a 16\bit divider the or function feeding the pe (program enable) input cannot be replaced by a wire or tie as the tc output of the least significant ep016a must also feed the ce input of the most significant ep016a. if the two tc outputs were or tied the cascaded count operation would not operate properly. because in the cascaded form the pe feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. maximizing ep016a count frequency the ep016a device produces 9 fast transitioning single ended outputs, thus v cc noise can become significant in situations w here all of the outputs switch simultaneously in the same direction. this v cc noise can negatively impact the maximum frequency of operation of the device. since the device does not need to have the q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. in addition, if only a subset of the q outputs are used in the system only those outputs should be terminated. not terminating the unused outputs will not only cut down the v cc noise generated but will also save in total system power dissipation. following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications. figure 8. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v
mc100ep016a http://onsemi.com 11 ordering information device package shipping ? mc100ep016afa lqfp-32 250 units / tray mc100ep016afag lqfp-32 (pb-free) 250 units / tray mc100ep016afar2 lqfp-32 2000 / tape & reel MC100EP016AFAR2G lqfp-32 (pb-free) 2000 / tape & reel mc100ep016amng qfn-32 (pb-free) 74 units / rail mc100ep016amnr4g qfn-32 (pb-free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d - ecl clock distribution techniques an1406/d - designing with pecl (ecl at +5.0 v) an1503/d - eclinps i/o spice modeling kit an1504/d - metastability and the eclinps family an1568/d - interfacing between lvds and ecl an1672/d - the ecl translator guide and8001/d - odd number counters design and8002/d - marking and date codes and8020/d - termination of ecl logic devices and8066/d - interfacing with eclinps and8090/d - ac characteristics of ecl devices
mc100ep016a http://onsemi.com 12 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae-ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 -t- -z- -u- t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac -ac- -ab- m 8x -t-, -u-, -z- t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 32 lead lqfp case 873a-02 issue c
mc100ep016a http://onsemi.com 13 package dimensions qfn32 5*5*1 0.5 p case 488am-01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 --- --- l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated fo r each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold sc illc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 mc100ep016a/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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